1. Field of the Invention
The invention relates to a semiconductor memory device comprising generating means for generating an internal clock signal for special mode, in particular, a semiconductor memory device such as a clock asynchronous DRAM (Dynamic Random Access Memory) for generating an internal clock signal for a special mode other than a normal mode.
2. Description of the Related Art
FIG. 17 is a block diagram showing a configuration of a clock asynchronous DRAM 100 of the related art.
Referring to FIG. 17, the DRAM 100 comprises the following interface terminals with external circuits, exclusive of a power supply terminal and a ground terminal:
(a) a clock input terminal T1 for in putting an external clock signal for controlling each operation;
(b) an address input terminal T2 for inputting an address signal for addressing memory cell arrays 20-1, 20-2, 20-3 and 20-4; and
(c) a data input and output terminal T3 for reading a data signal from the memory cell arrays 20-1 to 20-4 or writing data on the memory cell arrays 20-1 to 20-4.
Such external clock signals and external signals such as an the address signal, the data signal and the like are inputted to an internal circuit of the DRAM 100 through buffer amplifiers 2, 4, 5 and 6 and a clock generator 3.
First of all, the data signal is inputted to the data-in buffer amplifier 5. The data-in buffer amplifier 5 converts the data signal having a predetermined external signal level into the data signal having a predetermined internal signal level (having the same high level as the level of an operating power supply voltage supplied to the DRAM, namely, the so-called CMOS level). Then, the data-in buffer amplifier 5 writes the data signal having the internal signal level in the memory cell arrays 20-1 to 20-4 through sense refresh amplifiers and input and output controllers 23-1, 23-2, 23-3 and 23-4. On the other hand, the data signal, which is read out from the memory cell arrays 20-1 to 20-4 through the sense refresh amplifiers and input and output controllers 23-1 to 23-4, is inputted to the data-out buffer amplifier 6. The data-out buffer amplifier 6 converts the internal signal level of the data signal into the external signal level. Then, the data-out buffer amplifier 6 outputs the data signal having the external signal level through the data input and output terminal T3.
Moreover, the address signal is inputted to row decoders 21-1 to 21-4 and column decoders 22-1 to 22-4 through the address buffer amplifier 4. The row decoders 21-1 to 21-4 and the column decoders 22-1 to 22-4 decode the input address signal, respectively, and then, specify specific addresses on the memory cell arrays 20-1 to 20-4 by using the decoded addresses.
Furthermore, the external clock signal is inputted to the clock buffer amplifier 2 in a control clock signal generating circuit 1. The control clock signal generating circuit 1 comprises the clock buffer amplifier 2 and the clock generator 3. The clock buffer amplifier 2 converts the input external clock signal into a reference clock signal, and then, outputs the reference clock signal to the clock generator 3. The clock generator 3 converts the input reference clock signal into various types of control clock signals. Then, the clock generator 3 uses the control clock signals to execute a predetermined control process of the row decoders 21-1 to 21-4, the column decoders 22-1 to 22-4, the sense refresh amplifiers and input and output controllers 23-1 to 23-4 and an internal test controller (not shown).
FIG. 18 is a block diagram of a detailed configuration of the control clock signal generating circuit 1 of FIG. 17.
Referring to FIG. 18, the external clock signals include an external {overscore (RAS)} signal, an external {overscore (CAS)} signal, an external {overscore (WE)} signal and an external {overscore (OE)} signal. In the specification and drawings, an upper line of each signal indicates a low enable signal for activating the operation at low level. The {overscore (RAS)} signal is a row address control signal for controlling the latch of a row address, the amplification of data from the memory cell arrays, a refresh operation and an active or precharge operation of the overall DRAM chip. Moreover, the {overscore (CAS)} signal is a column address control signal for controlling the latch of a column address, a read operation of data from the memory cell arrays or a write operation of data in the memory cell arrays. Furthermore, the {overscore (WE)} signal is a write enable signal for controlling the read operation of data from the memory cell arrays or the write operation of data in the memory cell arrays. Furthermore, the {overscore (OE)} signal is an output enable signal for controlling the read operation of data from the memory cell arrays.
The external {overscore (RAS)} signal is inputted to an input buffer amplifier 7-1. The input buffer amplifier 7-1 converts the external {overscore (RAS)} signal having the external signal level into an internal {overscore (RAS)} signal having the internal signal level, and then, outputs the internal {overscore (RAS)} signal to the clock buffer amplifier 2. Moreover, the external {overscore (CAS)} signal is inputted to an input buffer amplifier 7-2. The input buffer amplifier 7-2 converts the external {overscore (CAS)} signal having the external signal level into an internal {overscore (CAS)} signal having the internal signal level, and then, outputs the internal {overscore (CAS)} signal to the clock buffer amplifier 2. Furthermore, the external {overscore (WE)} signal is inputted to an input buffer amplifier 7-3. The input buffer amplifier 7-3 converts the external {overscore (WE)} signal having the external signal level into an internal {overscore (WE)} signal having the internal signal level, and then, outputs the internal {overscore (WE)} signal to the clock buffer amplifier 2. Furthermore, the external {overscore (OE)} signal is inputted to an input buffer amplifier 7-4. The input buffer amplifier 7-4 converts the external {overscore (OE)} signal having the external signal level into an internal {overscore (OE)} signal having the internal signal level, and then, outputs the internal {overscore (OE)} signal to the clock buffer amplifier 2. Therefore, internal clock signals include the internal {overscore (RAS)} signal, the internal {overscore (CAS)} signal, the internal {overscore (WE)} signal and the internal {overscore (OE)} signal.
The clock buffer amplifier 2 and the clock generator 3 constitute a control clock generator 30. The clock buffer amplifier 2 generates a predetermined plurality of reference clock signals in accordance with the internal {overscore (RAS)} signal, the internal {overscore (CAS)} signal, the internal {overscore (WE)} signal and the internal {overscore (OE)} signal, and then, outputs the reference clock signals to the clock generator 3. The clock generator 3 generates and outputs the control clock signal in accordance with the input reference clock signals. The control clock signals include the row address control signal, the column address control signal, a write and read control signal, a refresh mode control signal and a test mode control signal, as shown in FIG. 18.
FIG. 19 is a circuit diagram showing a configuration of a control clock generator 30a for a normal mode, which is an example of the control clock generator 30 of FIG. 18. Referring to FIG. 19, the control clock generator 30a comprises two inverters INV1 and INV2, a NAND gate NAND1 and an AND gate AND1 with an inverted input terminal. The control clock generator 30a generates a {overscore (RASE)} signal for controlling a row system control circuit 24 in accordance with the internal {overscore (RAS)} signal and reference clock signals xcfx861 and xcfx862.
FIG. 20 is a circuit diagram showing a configuration of a control clock generator 30b for a special mode, namely, a {overscore (CAS)} before {overscore (RAS)} refresh mode (hereinafter referred to as a CbR mode), which is an example of the control clock generator 30 of FIG. 18. Referring to FIG. 20, the control clock generator 30b comprises two inverters INV3 and INV4 and two NAND gates NAND2 and NAND3. The control clock generator 30b generates a {overscore (CbR)} signal for controlling a CbR refresh control circuit 25 in accordance with the internal {overscore (CAS)} signal and the internal {overscore (RAS)} signal.
FIG. 21 is a timing chart of the external {overscore (RAS)} signal, the external {overscore (CAS)} signal, the external {overscore (WE)} signal and the external {overscore (OE)} signal during the read operation in the normal mode of the related art. In the clock asynchronous DRAM 100 of the related art, the normal mode operation such as the read operation or the write operation is defined by a specification of a data book of the DRAM in accordance with the edges and levels of the external clock signals including the external {overscore (RAS)} signal, the external {overscore (CAS)} signal and the external {overscore (WE)} signal, as shown in FIG. 21, for example.
FIG. 22 is a timing chart of the external {overscore (RAS)} signal, the external {overscore (CAS)} signal, the external {overscore (WE)} signal and the external {overscore (OE)} signal during a CbR refresh operation in the special mode of the related art. For example, as shown in FIG. 22, also in the case of the special mode such as the CbR mode or the like, the special mode operation is defined by the specification of the data book of the DRAM in accordance with the edges and levels of the external clock signals including the external {overscore (RAS)} signal and the external {overscore (CAS)} signal. In the CbR mode, the external {overscore (CAS)} signal is made to be low enable before the external {overscore (RAS)} signal is made to be low enable, this leads to that a condition for the special mode, namely, a condition for tCSR (in which the external {overscore (RAS)} signal becomes low enable after the external {overscore (CAS)} signal is set up) is satisfied.
As shown in FIG. 18, the external clock signals are inputted to the input buffer amplifiers 7-1 to 7-4 and are converted into the internal clock signals by the input buffer amplifiers 7-1 to 7-4. Then, the internal clock signals are converted into the control clock signals by the control clock generator 30. The control clock signals are simultaneously outputted to the control circuit for the normal mode and the control circuit for the special mode. When a noise is superimposed on the external clock signal in the normal mode operation, the normal mode may be thus switched to the special mode, and consequently an unexpected operation (malfunction) may occur.
FIG. 23 shows an example of occurrence of timing of the CbR mode due to a noise superimposed on the external {overscore (RAS)} signal in the data read operation. When positive noise (noise having such a level as the level changing in a positive direction with respect to a signal level) is superimposed on the external {overscore (RAS)} signal and the external {overscore (CAS)} signal so as to satisfy the above-mentioned condition for tCSR in a period of time in which both of the external {overscore (RAS)} signal and the external {overscore (CAS)} signal have a low level, the condition for the CbR mode holds, and thus, the refresh operation starts. A problem is that memory cell data is destroyed due mainly to bit activation executed without following a regular procedure, but a cause of the problem somewhat varies according to the time of the condition for tCSR. Moreover, as this example of FIG. 23 shows, such an entry into the special mode as interrupting the normal mode operation (leading to abnormal stop) is more fatal than the case of noise superimposed on an access path. That is, because most of noise is likely to disappear on account of properties of the access path that the noise superimposed on the access path passes through many gates before an end circuit operates. On the other hand, the entry into the special mode is determined after passing through a few gates following the input terminal for the external clock signal, and therefore, the entry into the special mode is sensitive to the noise.
In the circuit configuration of the DRAM 100 of the related art, the normal mode and the special mode are distinguished from each other in accordance with only the edges and levels of the external clock signals. Thus, the noise superimposed on the external clock signal may confuse the distinction between the normal mode and the special mode.
An essential object of the present invention is to provide a semiconductor memory device capable of reducing or preventing any switching to the special mode from the normal mode operation due to noise on an external clock without affecting any influence on an access time of the semiconductor memory device.
According to the aspect of the present invention, there is provided a semiconductor memory device comprising:
input buffer amplifiers for converting a plurality of external clock signals into a plurality of internal clock signals each having an internal signal level, respectively;
a signal generating circuit for generating control clock signals for controlling an operation of the semiconductor memory device in accordance with the plurality of internal clock signals; and
generating means having a time response characteristic gently changing according to a change in an input signal, the generating means generating an internal clock signal for a different special mode from a normal mode associated with either one of reading and writing of data from and in the semiconductor memory device in accordance with at least one of the plurality of external clock signals.
In the above-mentioned semiconductor memory device, the generating means is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, the generating means is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, the generating means are preferably provided for at least two of the plurality of external clock signals, and one of a plurality of generating means is provided in the input buffer amplifier, while another of the plurality of generating means is the noise filter provided so as to follow the input buffer amplifier.
In the above-mentioned semiconductor memory device, the plurality of external clock signals preferably include an external {overscore (RAS)} signal and an external {overscore (CAS)} signal, and the generating means are provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal.
In the above-mentioned semiconductor memory device, the plurality of external clock signals preferably include an external {overscore (RAS)} signal, an external {overscore (CAS)} signal and an external {overscore (WE)} signal, and the generating means are provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal and the external {overscore (WE)} signal.
In the above-mentioned semiconductor memory device, the plurality of external clock signals preferably include an external {overscore (RAS)} signal, an external {overscore (CAS)} signal, an external {overscore (WE)} signal and an external {overscore (OE)} signal, and the generating means are provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal, the external {overscore (WE)} signal and the external {overscore (OE)} signal.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, the generating means provided for the external {overscore (RAS)} signal is preferably provided in the input buffer amplifier, and the generating means provided for the external {overscore (CAS)} signal is a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, the generating means provided for the external {overscore (RAS)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal. Further, the generating means provided for the external {overscore (CAS)} signal is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal and the external {overscore (WE)} signal is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal and the external {overscore (WE)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably provided in the input buffer amplifier. Further, the generating means provided for the external {overscore (WE)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal. Further, the generating means provided for the external {overscore (WE)} signal is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal, the external {overscore (WE)} signal and the external {overscore (OE)} signal is preferably provided in the input buffer amplifier.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal, the external {overscore (CAS)} signal, the external {overscore (WE)} signal and the external {overscore (OE)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably provided in the input buffer amplifier. Further, each of the generating means provided for the external {overscore (WE)} signal and the external {overscore (OE)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal.
In the above-mentioned semiconductor memory device, each of the generating means provided for the external {overscore (RAS)} signal and the external {overscore (CAS)} signal is preferably a noise filter provided so as to follow the input buffer amplifier, where the noise filter delays the change in the input signal and outputs a delayed signal as an output signal. Further, each of the generating means provided for the external {overscore (WE)} signal and the external {overscore (OE)} signal is preferably provided in the input buffer amplifier.
Accordingly, the noise superimposed on the external clock signal can be delayed and reduced, and thus, the influence of the noise can be remarkably reduced. It is therefore possible to reduce, relax or prevent a malfunction due to the noise superimposed on the external clock signal, more particularly, such an entry into the special mode as interrupting the normal mode operation (leading to abnormal stop) such as the read or write operation or the like.
More particularly, the above-mentioned noise filter can eliminate both of the positive noise changing in the positive voltage direction and the negative noise changing in the negative voltage direction, which are superimposed on the external clock signal.